Non-Volatile Memory (NVM) devices are subject to failures, such as word-line-to-substrate and word-line-to-word-line shorts, and require early detection in order to avoid data loss. Examples of prior art techniques are provided below.
U.S. Pat. No. 7,212,454, to Kleveland, et al., whose disclosure is incorporated herein by reference, describes a method and apparatus for programming a memory array. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line.
U.S. Pat. No. 8,379,454, to Kochar, et al., whose disclosure is incorporated herein by reference, describes techniques and corresponding circuitry for detection of broken word lines in a memory array. An “inter-word line” comparison where a program loop counts of different word lines are compared in order to determine whether a word line may be defective. A number of programming pulses needed for the cells along a word line WLn is compared to the number needed for a preceding word line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value.
U.S. Pat. No. 6,545,910, to Byeon, et al., whose disclosure is incorporated herein by reference, describes a non-volatile semiconductor memory device having word line defect check circuit. The non-volatile semiconductor memory device includes: a memory cell array including a plurality of cell array blocks including a plurality of cell strings that consist of floating gate memory cell transistors that its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines. A word line short check circuit inputs different levels of voltage to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and generates a short sense signal that indicates whether short between adjacent word lines has occurred by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.
U.S. Pat. No. 6,813,183, to Chevallier, et al., whose disclosure is incorporated herein by reference, describes a method and system for externally triggered leakage detection and repair in a flash memory device. In an embodiment the method includes operating a flash memory device to store data in a number of flash cells and initiating an operation to detect or repair leaky flash cells in the flash memory device by coupling one or more selected signals to the flash memory device from a source external to the flash memory device.